The present invention relates generally to device fabrication and, in particular, to techniques for reducing or eliminating silicon defect induced failures, such as latch-up, in complementary metal-oxide-semiconductor (CMOS) and other integrated circuits.
CMOS integrated circuit chips fabricated with silicon can exhibit a phenomenon known as latch-up during which the integrated circuit is short-circuited and draws excessive current and power from the power supply. Latch-up can result in thermal destruction of the chip.
A typical CMOS structure includes several bi-polar transistors that constitute a potential n-p-n-p device that can latch-up under certain conditions. One such bi-polar structure results from a vertical p-n-p structure formed by the p+ drain/source regions of the p-channel metal-oxide-semiconductor field-effect-transistor (MOSFET), the n-tub and the p-substrate. A lateral n-p-n structure can result from the n-tub, the p-substrate and the n+ drain/source regions of the n-channel MOSFET. Additionally, the inclusion of input protection diodes (n+p to the substrate and p+n to the n-well) with p+ contacts to the substrate and n+ contacts to the tub can further complicate the situation.
A necessary condition for latch-up is that the product of the n-p-n and p-n-p transistor gains exceeds unity. Furthermore, the end junctions of the structure must become forward biased. Under normal operating conditions, the latter condition does not occur. However, it may occur due to transient signals or in a high radiation environment. Additionally, the V.sub.DD power supply and the input circuit must be capable of providing the holding current for the p-n-p-n device. Under those conditions, The p-n-p-n device can exhibit positive feedback and behave like a short circuit. The signal feeds upon itself and grows exponentially until it turns into a large current short-circuit path.
One technique for reducing the occurrence of latch-up failure involves providing a heavily doped buried layer beneath a more-lightly doped layer upon which the remainder of the integrated circuit is fabricated. The heavily doped buried layer increases the holding current and voltage as well as the critical current to prevent the occurrence of latch-up during normal operation of the semiconductor device. The buried layer shorts the adjacent p-n junctions so that they cannot become forward biased. Positive feedback, therefore, is inhibited, and high current and power consumption are avoided.
Although a heavily doped buried layer can reduce the occurrence of latch-up, various defects in the buried layer, such as in-the-range defects or boron-enhance stacking faults, can propagate and become redistributed in other device layers during subsequent fabrication steps performed at elevated temperatures. Such elevated temperature steps include, for example, oxidation, activation and annealing processes. The propagation of defects from the buried layer to other device layers during the fabrication process reduces the overall yield and can reduce device performance and reliability.